DFT Engineer
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Job Description
Senior DFT Engineer leading end-to-end DFT strategy for complex SoCs at Niobium Microsystems. Overseeing architecture, integration, and validation processes within the team.
Responsibilities:
- Own and drive end-to-end DFT strategy for complex SoCs, from architecture through silicon bring-up
- Serve as DFT lead for major subsystems or full-chip execution
- Define and implement DFT architecture including scan, compression, and MBIS
- Establish DFT insertion strategies at RTL and/or netlist stages
- Drive scan chain stitching, compression insertion, and clock/reset domain handling
- Collaborate with physical design to meet timing, routing, and signoff requirements
- Execute ATPG and fault simulation to achieve high fault coverage targets
- Develop and validate test patterns for scan, BIST, and low-power modes
- Track and drive DFT sign off criteria including coverage, waivers, and escape analysis
- Partner with test engineering to translate patterns to ATE platforms
- Support silicon bring-up, debug failing patterns, and perform yield analysis
- Conduct shmoo analysis and root-cause failures
- Drive DFT methodology improvements, automation, and flow optimization
- Develop scripts and infrastructure for scalable DFT flows
- Represent DFT in cross-functional reviews and program milestones
Requirements:
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field
- 8+ years of hands-on DFT experience in ASIC or SoC design
- Strong expertise in scan architecture, ATPG, compression techniques, and MBIST
- Experience driving DFT from RTL through GDSII, including physical design collaboration
- Hands-on experience with ATE bring-up and post-silicon debug
- Proficiency in scripting (Tcl, Python) for automation and flow development
Benefits:
- Competitive salaries
- Employer paid health care
- Employer contribution to health savings account
- Flexible time off
- Flexible work location with remote options
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