Senior/Lead ASIC Engineer
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Job Description
Lead ASIC DFT Engineer responsible for end-to-end DFT architecture and implementation for complex ASIC/SoC designs. Collaborating across multiple teams and mentoring junior engineers.
Responsibilities:
- Lead DFT architecture, implementation & sign-off
- Drive scan insertion, scan chains & compression flows
- Own MBIST/LBIST integration and debug
- Perform silicon debug, failure analysis & root cause
- Develop DFT constraints (SDC) & timing analysis
- Support ATPG generation, simulation & coverage closure
- Work on JTAG, boundary scan, iJTAG
- Collaborate across RTL, PD, STA, validation teams
- Mentor junior engineers
- Develop automation scripts (TCL/Perl/Python)
Requirements:
- 10+ years in ASIC DFT (hands-on)
- Strong DFT fundamentals & fault models knowledge
- Expertise in scan, ATPG, MBIST, JTAG, debug
- Experience with Synopsys / Cadence / Siemens tools
- Post-silicon validation experience
- Large SoC & hierarchical DFT exposure
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