Senior Mixed-Signal Verification Engineer
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Job Description
Senior Mixed-Signal Verification Engineer developing behavioral models and verification methodologies for advanced mixed-signal SoCs. Collaborating in a fast-paced environment to support satellite technology.
Responsibilities:
- Develop high-level behavioral models for analog and mixed-signal IP (ADCs, DACs, PLLs, LDOs, RF front-end blocks, biasing, amplifiers, etc.)
- Create abstracted models using Verilog, Verilog-AMS, or SystemVerilog
- Develop regression infrastructure and mixed-signal testbenches enabling co-simulation (digital + analog)
- Integrate AMS models into digital verification environments (UVM-based)
- Define and build the mixed-signal verification methodology for top-level SoC and subsystem verification
- Support architectural exploration through early-phase modeling and system-level simulations
- Collaborate with analog/RF designers to capture real-world analog behaviors and map them into accurate behavioral abstractions
- Work with digital and verification teams to ensure seamless integration of AMS models
- Provide modeling and verification insights during architectural reviews, PDR/CDR, and silicon bring-up
- Act as technical leader and subject-matter expert.
Requirements:
- M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or related field
- 5+ years of experience in analog/mixed-signal modeling and/or AMS verification
- Hands-on experience with SystemVerilog, Verilog-AMS, wreal/RNM, or equivalent modeling languages
- Strong understanding of analog/mixed-signal circuits (PLLs, LDOs, ADC/DACs, RF/IF paths, clocking, amplifiers)
- Experience with mixed-signal co-simulation environments (Cadence AMS Designer, Synopsys VCS AMS, or similar)
Benefits:
- Comprehensive benefits package including paid time off
- Medical/dental/vision coverage
- Life insurance
- Paid parental leave
- Many other perks
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