Senior ASIC Verification Engineer
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Job Description
Senior ASIC Verification Engineer specializing in UVM and PCIe at BTA Design in Canada. Collaborating with verification professionals for complex, high-speed interface designs.
Responsibilities:
- Join a team verifying blocks, subsystems, or entire chips—with an emphasis on high-speed interfaces and networking IP
- Support the verification lead on project planning and management of front-end development activities
- Develop test and coverage plans, as well as verification environment architectures, using SystemVerilog and UVM
- Capture test coverage points and write targeted and constrained-random test cases
- Employ constrained-random verification approaches and assertion-based verification where appropriate
- Support silicon and lab bring-up with directed tests, especially for high-speed interface validation
- Perform and analyze both code and functional coverage to drive closure
Requirements:
- 8+ years of experience in ASIC verification
- Deep expertise in Verilog, SystemVerilog, and scripting languages
- Proven experience with the responsibilities listed above
- Significant experience with OVM/UVM methodologies
- Experience developing test and coverage plans from scratch
- Experience architecting and developing multiple SV/UVM verification environments, both from scratch and through re-use, would be ideal
- Strong expertise in constrained-random verification techniques, assertions, and functional coverage
- Demonstrated experience verifying high-speed interfaces and networking protocols such as SERDES and other high-speed PHYs, PCIe, Ethernet, OTN, SONET, InfiniBand, or similar high-bandwidth interconnects
- Experience with video processing, GPUs, or AI is an additional asset
- Team-oriented with excellent interpersonal and communication skills.
Benefits:
- company bonus and benefits plan
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