Design Verification Engineer
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Job Description
Design Verification Engineer validating chiplet infrastructure IP for AI/HPC systems at TylSemi. Developing SystemVerilog/UVM environments, tests, coverage models, assertions, and automation.
Responsibilities:
- Develop and execute verification test plans for IPs, subsystems, and SoC components
- Create and maintain SystemVerilog/UVM-based verification environments
- Write directed and constrained-random test cases to validate design functionality
- Develop functional coverage models and assist in coverage closure activities
- Debug simulation failures and collaborate with design engineers to resolve issues
- Write assertions (SVA) to improve design checking and verification quality
- Participate in regression execution, result analysis, and reporting
- Support IP integration and subsystem-level verification activities
- Learn and apply industry-standard verification methodologies and best practices
- Contribute to automation scripts for regression, reporting, and verification productivity
- Work closely with Design, Architecture, and Software teams to understand requirements and verify functionality
Requirements:
- Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field
- 5+ years of experience in Design Verification or Digital Design
- Strong understanding of digital design fundamentals and computer architecture
- Knowledge of Verilog/SystemVerilog
- Knowledge of UVM methodology
- Knowledge of simulation and debugging concepts
- Knowledge of functional and code coverage
- Basic scripting in Python, Perl, Shell, or TCL
- Familiarity with verification tools from Synopsys, Cadence, or Siemens EDA
- Good analytical and debugging skills
- Understanding of common bus protocols such as AXI, APB, AHB, PCIe, or Ethernet is a plus
- Internship or academic project experience in ASIC/SoC verification is preferred
- Exposure to SystemVerilog assertions (SVA) is preferred
- Knowledge of constrained-random verification techniques is preferred
- Experience with Python-based automation is preferred
- Understanding of AI, HPC, or Networking architectures is a plus
- Familiarity with Git or other version-control systems is preferred
- Strong communication and teamwork abilities
Benefits:
- Remote-friendly work arrangement
- Opportunity to work with a global team
- Opportunity to work on cutting-edge SoCs and IPs for AI, HPC, and Networking
- Opportunity to contribute to next-generation semiconductor technologies
- Opportunity to work with experienced verification engineers and architects
- Opportunity to work on consequential silicon infrastructure for AI
- Strategic investors, committed capital, and a clear path to revenue
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