Design Verification Engineer
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Job Description
Design Verification Engineer developing SystemVerilog/UVM environments for Altera’s high-speed SerDes FPGA IP. Debugging simulations and verifying PCIe, Ethernet, and other interface technologies.
Responsibilities:
- Develop and maintain SystemVerilog/UVM verification environments for SerDes and PHY blocks
- Write testbenches, functional coverage models, and assertions
- Run simulations, analyze failures, and debug both RTL and testbench issues
- Collaborate with design, architecture, and analog teams on block-level and top-level verification
- Verify high-speed SerDes IP used in PCIe, Ethernet, and other industry-standard interfaces
Requirements:
- BSc in Electrical Engineering, Computer Engineering, or equivalent
- 0–5 years of experience in digital design or verification (internships, academic projects, or industry)
- Working knowledge of SystemVerilog and basic familiarity with UVM concepts
- Solid digital design fundamentals: synchronous logic, FSMs, pipelining, clock domain crossing
- Strong analytical and debug mindset — you enjoy getting to the bottom of a problem
- Good communication skills in English (spoken and written)
- Candidates should preferably be able to reside in Iași
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