Hardware Engineer – RTL Implementation, Evaluation Workflows
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Job Description
Hardware engineers participating in paid remote interviews on RTL implementation and verification workflows. Providing expert feedback to Terac, a platform connecting AI researchers with vetted human experts.
Responsibilities:
- Participate in a remote interview about typical hardware design processes
- Walk through RTL implementation and hardware description approaches
- Review and react to automated evaluation scenarios
- Demonstrate hardware description workflows through screen sharing
- Describe a recent complex hardware verification challenge
- Provide feedback on current workflows and tooling gaps
- Discuss challenges with current verification tools
Requirements:
- Experienced hardware engineer specializing in RTL design and implementation
- Professional experience in hardware engineering or RTL design
- Hands-on experience with hardware description languages (Verilog, VHDL, or SystemVerilog)
- Familiarity with automated evaluation and verification workflows
- Comfortable discussing technical design choices in a remote interview
- Open to ASIC designers, FPGA engineers, hardware verification specialists, and system-on-chip (SoC) architects
- Must be based in the United States
Benefits:
- Paid study/interview compensation of $147 per hour
- Remote interview participation
- Interview link sent within minutes of applying
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